Several of today's computer system architectures employ a source strobed bus and method to transfer data between devices. In a typical source strobe architecture, the transmitting device transmits to the receiving device a clock signal/strobe and data. The strobe alerts the receiving device that valid data has been transmitted over the bus. Computer bus architectures such as AGP (accelerated graphics port), DDR SDRAM (double data rate synchronous dynamic random access memory), and RDRAM (Rambus random access memory) utilize source strobes in this manner.
A source strobe data bus is an efficient mechanism for transferring large amounts of data on a minimum number of pins or connections between devices. Often times at least one of the devices connected to the source strobed bus is also connected to another bus, such as an industry standard bus. Examples of industry standard buses includes the PCI (peripheral component interconnect) and PCI-X (peripheral component interconnect extended) buses. Thus, a device may receive data from the source strobed bus, process the data and then transmit the processed data over the industry standard bus to another device.
There will be times, however, when the device connected to the additional bus is unable to accept a data transfer from the source strobe bus. This may arise, for example, when the ordering rules or bus protocol of the additional bus dictates that the receiving device should not receive data at that time. In addition, there may be times when the receiving device has become disconnected from the source strobed bus or is otherwise incapable of acting on the transfer due to a power-down or other condition. This inability to accept the transfer must be communicated to the transferor of the data can disconnect the transfer as soon as possible. Once disconnected, the transferor must be able to reschedule (if the target is connected, but not ready to accept the transfer at the moment) or abort/cancel (if the target is disconnected, etc.) the data transfer to avoid unnecessary delays, erroneous data processing or a deadlock within the system.
Unnecessary delays, erroneous data processing and deadlocking conditions would severely impact system performance. Thus, there is a desire and need to disconnect transfers on a source strobe bus in an efficient and timely manner so that system performance is not adversely impacted when a receiving device cannot accept a data transfer.
At noted earlier, large amounts of data can be transferred over the source strobed bus. As such, there will be times when the receiving device is incapable of completing a data transfer. This may arise, for example, when the input buffers of the receiving device become full and are no longer capable of receiving more data. If this happens, data transferred to the receiving device will be dropped, which may lead to erroneous processing or deadlock conditions within the system.
Other times, the receiving device may not have an outlet for the data (i.e., the device/bus the receiving device is connected to cannot accept data due to e.g., a bottleneck condition). Although the receiving device can accept the data from the transferor, the receiving device will have no where to send the data. The inability to complete the data transfer must be communicated to the transferor so that the transferor can pace the transfer in a manner in that allows the receiving device time to complete the transfer. Thus, there is a desire and need to pace transfers on a source strobe bus in an efficient and timely manner so that system performance is not adversely impacted when a data transfer must be stalled.